This application claims the priority benefit of Taiwan application serial no. 87104445, filed Mar. 25, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to electrostatic discharge (ESD) protection circuits, and more particularly, to a gate-voltage controlled ESD protection circuit for use in an integrated circuit (IC) device for the purpose of protecting the internal circuit of the IC device against ESD stress.
2. Description of Related Art
In the fabrication of semiconductor IC devices, electrostatic discharge (ESD) is a major problem that can cause damage to the internal circuit of the IC device. One solution to this problem is to incorporate an on-chip ESD protection circuit on the input/output (I/O) pads of CMOS (complementary metal-oxide semiconductor) devices. However, as semiconductor fabrication technologies have advanced to the deep-submicron level, the conventional ESD protection circuit is no longer able to provide adequate ESD robustness. This problem will be illustratively depicted in the following with reference to FIGS. 1-2.
FIG. 1 is a schematic diagram of a conventional ESD protection circuit. As shown, this conventional ESD protection circuit is connected to an input pad (IP) 12 and includes a field oxide device (FOD) F1, an NMOS (N-type metal-oxide semiconductor) transistor N1, a resistor R1, and an inverter 10. The NMOS transistor N1 is connected in such a manner that its gate is connected to the ground power line VSS (thus referred to as a gate-grounded NMOS transistor) and is specifically designed to operate in the breakdown mode. When an ESD stress appears at the IP 12, the resulting ESD current can bypass through the gate-grounded NMOS transistor N1 to the ground power line VSS. To allow the gate-grounded NMOS transistor N1 to provide this ESD protection effect, the breakdown voltage of the gate-grounded NMOS transistor N1 should be smaller than the breakdown voltage of the gate oxide layer in the inverter 10. In other words, the breakdown voltage of the gate-grounded NMOS transistor N1 decreases as the channel length is shortened. However, a short channel length will make the gate-grounded NMOS transistor N1 undesirably more vulnerable to ESD stress. The provision of the resistor R1 can suppress the ESD current flowing through the gate-grounded NMOS transistor N1. Moreover, the FOD F1 can help drain part of the ESD current from the IP 12 to the ground power line VSS. The FOD F1 is preferably constructed on a non-lightly doped drain (LDD) structure, which allows the FOD F1 to be longer in channel length than the gate-grounded NMOS transistor N1 so as to be capable of withstanding larger ESD currents.
A negative ESD voltage applied to the IP 12 causes the gate-grounded NMOS transistor N1 to produce a parasite diode current. A positive ESD voltage applied to the IP 12 causes the gate-grounded NMOS transistor N1 to produce an NPN avalanche breakdown current, thus causing a large potential drop across the resistor R1. As a result of this, the FOD F1 is switched to the conductive state. If the FOD F1 is designed to be longer in channel length than the gate-grounded NMOS transistor N1, it will be also larger in breakdown voltage than the gate-grounded NMOS transistor N1. Therefore, the level of the breakdown voltage of the FOD F1 can be close or even larger than that of the gate oxide layer in the inverter 10. If the IC device is further downsized, the gate oxide layer in the inverter 10 will be correspondingly made thinner. As a result, the inverter 10 would be subjected to a breakdown voltage before the NPN or PNP conduction takes place in the ESD protection circuit. The ESD protection circuit is therefore reduced in its ESD robustness to provide adequate ESD protection to the downsized IC device.
FIG. 2 is a schematic diagram of another conventional ESD protection circuit. As shown, this conventional ESD protection circuit is connected to an input pad (IP) 22 and includes a PMOS (P-type metal-oxide semiconductor) transistor P2, an NMOS (N-type metal-oxide semiconductor) transistor N2, a resistor R2, and an inverter 20. The PMOS transistor P2 is connected in such a manner that its gate and source are connected to the system power line VDD, while the NMOS transistor N2 is connected in such a manner that its gate and source are connected to the ground power line VSS.
A positive ESD voltage applied to the IP 22 causes the PMOS transistor P2 to produce a parasite diode current. If a negative ESD voltage is applied, it subjects the PMOS transistor P2 to a PNP avalanche breakdown current. This causes the source, drain, and substrate of the PMOS transistor P2 to be equivalently formed into a PNP structure, as indicated by the dashed box B1 in FIG. 2. If the negative ESD voltage is overly large in magnitude, it will cause an avalanche breakdown to this PNP structure B1.
On the other hand, a negative ESD voltage applied to the IP 22 causes the NMOS transistor N2 to produce a parasite diode current. However, in the event that a positive ESD voltage is applied, it subjects the NMOS transistor N2 to an NPN avalanche breakdown current. This causes the source, drain, and substrate of the NMOS transistor N2 to be equivalently formed into an NPN structure, as indicated by the dashed box B2 in FIG. 2. If the positive ESD voltage is overly large in magnitude, it will cause an avalanche breakdown to this NPN structure B2.
If the design for the IC device incorporating the foregoing ESD protection circuit of FIG. 2 is further downsized, the gate oxide layer in the inverter 20 is correspondingly made thinner. This makes the breakdown voltage of the PMOS transistor P2 and the NMOS transistor N2 close to or even greater than the breakdown voltage of the gate oxide layer in the inverter 20. As a bad consequence of this, the inverter 20 is be subjected to breakdown before the NPN or PNP structure in the ESD protection circuit is switched into the conductive state, thus causing the ESD protection circuit to fail to provide the desired ESD protection.
It is therefore an objective of the present invention to provide a gate-voltage controlled ESD protection circuit, which can help the PMOS and NMOS transistors in the ESD protection circuit provide the desired ESD protection without being affected by breakdown of the thin oxide layer in the inverter.
In accordance with the foregoing and other objectives of the present invention, a gate-voltage controlled ESD protection circuit is provided. The ESD protection circuit of the invention is coupled between an IP and an IC device having an inverter coupled to the internal circuit for the purpose of protecting the IC device against ESD stress. The ESD protection circuit comprises a resistor, a PMOS transistor, a first potential drop subcircuit, an NMOS transistor, and a second potential drop subcircuit. The resistor has a first end connected to a common node connected to the IP and a second end connected to the input end of the inverter. The PMOS transistor has its source connected to a first power line and drain connected to the common node. The first potential drop subcircuit has a positive end connected to the gate of the PMOS transistor and a negative end connected to the common node, which can be turned into conductive state when a negative ESD voltage lower in magnitude than a predetermined level is applied to the IP, causing the PMOS transistor to be switched into conductive state. The NMOS transistor has its source connected to a second power line and its drain connected to the common node. The second potential drop subcircuit has a positive end connected to the common node and a negative end connected to the gate of NMOS transistor, and which can be switched to the conductive state when a positive ESD voltage higher in magnitude than a predetermined level is applied to the IP, causing the NMOS transistor to be switched into conductive state.